VHDL Functions and CASE (switch) implementations on the Papilio One platform

I have been further investigating the Papilio One platform and wanted to share my newest achievement which involves a simple function and a case statement.

To begin with a simple function implementation, here is the basic prototype for VHDL:

my_function : process (input1, input2, ...)
begin
output <= input1 AND input2;
end process

There aren’t that many differences between this and a function declaration in C/C++, Java, etc. The second concept I learned in VHDL are the CASE statements which are basically a switch statement in C/C++. They were particularly useful for this implementation as I could turn on and off any bars based on the input. Here is my CASE statement implementation:

CASE switches(7 downto 0) IS
WHEN "00000000" =>
segments <= "0000000"; -- Fully Lit display LEAVE AS IS!
dp <= '0'; WHEN "00000001" => -- When switch one is triggered
segments <= "1111001"; -- Shows 1
dp <= '1'; -- Removes the dot WHEN "00000010" => -- When switch two is triggered
segments <= "0100100"; -- Shows 2
dp <= '1'; WHEN "00000100" => -- When switch three is triggered
segments <= "0110000"; -- Shows 3
dp <= '1'; WHEN "00001000" => -- When switch four is triggered
segments <= "0011001"; -- Shows 4
dp <= '1'; WHEN "00010000" => -- When switch five is triggered
segments <= "0010010"; -- Shows 5
dp <= '1'; WHEN "00100000" => -- When switch six is triggered
segments <= "0000010"; -- Shows 6
dp <= '1'; WHEN "01000000" => -- When switch seven is triggered
segments <= "1111000"; -- Shows 7
dp <= '1'; WHEN "10000000" => -- When switch eight is triggered
segments <= "0000000"; -- Shows 8
dp <= '1'; WHEN OTHERS =>
segments <= "0000000"; -- Remove dot
dp <= '1';
END CASE;

Note: I could have implemented many more combinations to display letters, numbers or other characters on the display by simply changing the addresses of outputs to be pulled high. In other words if you know which pin is associated with which LED, you can simply write a CASE statement to turn any of them off.

Here is a short video of what this looks like:

I hope you enjoyed my video, see you next time with some more VHDL implementations.