# Full-Adder implementation on the Papillio One

Hi everyone,

I just finished the first exercise for the Papilio One and wanted to share it with you. I am using Mike Field’s guide for FPGA programming, so I would like to give him credit for his work. The code I have used is partially explained in his book and was only modified by me to achieve a full adder.

Here is what the code for the 5 bits looks like. Each result bit is the LED you will see in my video.

`result(0) <= x(0) XOR y(0);`

carry(0) <= x(0) AND y(0);

result(1) <= x(1) XOR y(1) XOR carry(0);

carry(1) <= (x(1) AND y(1)) OR (carry(0) AND X(1)) OR (carry(0) AND Y(1));

result(2) <= x(2) XOR y(2) XOR carry(1);

carry(2) <= (x(2) AND y(2)) OR (carry(1) AND X(2)) OR (carry(1) AND Y(2));

result(3) <= x(3) XOR y(3) XOR carry(2);

carry(3) <= (x(3) AND y(3)) OR (carry(2) AND X(3)) OR (carry(2) AND Y(3));

result(4) <= carry(3);

Basically this simply performs a logic check for every single bit. The first one is simple to understand. 0+0 = 0, 0+1=1, 1+0=1,1+1=0 (and a carry) and therefore we only have an XOR function for the first bit. The carry obviously only happens when both first bits are 1 so that explains the AND function. Further down the line you need to consider the current bits as well as the previous carry bit. I will let you walk through the code.

Here is a short video of me showing the full adder in practice:

Feel free to share this video and if you got any questions, post here or send me a message through the “Contact Form”. Also if you have any interesting projects that you made on the Papilio, feel free to share them also; I’m always looking for inspiration.